`timescale 1ns / 1ps
/*
 Copyright 2020 Sean Xiao, jxzsxsp@qq.com
 
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
 You may obtain a copy of the License at
 
 http://www.apache.org/licenses/LICENSE-2.0
 
 Unless required by applicable law or agreed to in writing, software
 distributed under the License is distributed on an "AS IS" BASIS,
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and
 limitations under the License.
 */

module csr_mie
(
    input sys_clk,

    input i_acc_dis,

    input [ 11: 0 ] i_csr_addr,
    input [ 31: 0 ] i_csr_val,
    input i_csr_wen,

    output [ 31: 0 ] o_mie,
    output o_meie,
    output o_msie,
    output o_mtie,

    input rst_n
);

/*
mie:   Machine Interrupt Enable Register     WR

XLEN-1   12   11     10     9      8      7      6      5      4      3      2      1      0     
------------------------------------------------------------------------------------------------
WPRI       | MEIE | WPRI | SEIE | UEIE | MTIE | WPRI | STIE | UTIE | MSIE | WPRI | SSIE | USIE |
------------------------------------------------------------------------------------------------

*/
wire wbck_csr_wen = i_csr_wen & ( ~i_acc_dis );
//0x304 MRW o_mie Machine interrupt-enable register.
wire sel_mie = ( i_csr_addr == 12'h304 );
wire wr_mie = sel_mie & i_csr_wen;
wire mie_ena = wr_mie & wbck_csr_wen;
wire [ 31: 0 ] mie_r;
wire [ 31: 0 ] mie_nxt;

assign mie_nxt[ 31: 12 ] = 20'b0;
assign mie_nxt[ 11 ] = i_csr_val[ 11 ]; //o_meie
assign mie_nxt[ 10: 8 ] = 3'b0;
assign mie_nxt[ 7 ] = i_csr_val[ 7 ]; //o_mtie
assign mie_nxt[ 6: 4 ] = 3'b0;
assign mie_nxt[ 3 ] = i_csr_val[ 3 ]; //o_msie
assign mie_nxt[ 2: 0 ] = 3'b0;

yue_dfflr #( 32 ) mie_dfflr ( mie_ena, mie_nxt, mie_r, sys_clk, rst_n );


assign o_mie = mie_r;

assign o_meie = o_mie[ 11 ];
assign o_mtie = o_mie[ 7 ];
assign o_msie = o_mie[ 3 ];



endmodule
